1. Field of the Invention
Example embodiments of the present invention relate to a method of forming a pattern, and more particularly, to a method of forming a self-aligned double pattern.
2. Description of Related Art
Due to an increased demand for highly integrated semiconductor memory devices, techniques of integrating more devices onto a small area have become strongly relied upon. The integration of many devices onto a small area involves downscaling the devices to be formed on a semiconductor substrate. However, the downscaling of the devices has a limit. The wavelength of a light source used in a photolithography process, which determines the dimensions of a device, is reaching technical limitations.
A KrF eximer laser and an ArF eximer laser may be used as light sources during the photolithography process. The ArF eximer laser has a wavelength of 193 nm and a feature size of 0.07 to 0.15 μm, and the KrF eximer laser has a wavelength of 248 nm and a feature size of 0.13 to 0.25 μm. In addition to KrF and ArF, a mercury lamp, for example, an I-line or a G-line, may be used as a light source during the photolithography process.
By using a light source with a short wavelength, fine patterns may be formed due to higher resolution. However, currently there is no available photoresist, which can absorb a light source having a short wavelength and enable chemical amplification. To make use of a light source with a short wavelength, it is necessary to develop photoresist that is photosensitive to short wavelength.
To overcome this drawback, a method of forming a self-aligned double pattern has been developed. The method may utilize the resolution capabilities of a photolithography apparatus to form a pattern twice as integrated as a conventional pattern.
For example, there is a first conventional method of forming a metal pattern. The method may include sequentially forming a first conductive layer pattern, a first insulating layer pattern, a second conductive layer pattern, and a second insulating layer pattern on a substrate. Etching may be performed using the second insulating layer pattern as an etch mask. A third insulating layer pattern may fill spaces between the second insulating layer patterns formed by the etching process. The second conductive layer pattern may be formed between the first conductive layer pattern with a pitch equal to the resolution limit, thereby completing a self-aligned double pattern.
A second conventional method may include forming an interconnection pattern for a semiconductor device. A first interconnection pattern may be formed, and an insulating layer may be coated on and between the first interconnection patterns. The insulating layer may be formed to a thickness equal to the depth of an over-etched portion under the first interconnection pattern. Also, an interconnection material layer may be formed on the insulating layer. A planarization process may be performed on the interconnection material layer, thereby forming a second interconnection pattern between the first interconnection patterns.
There is also a third conventional method for pitch reduction. A photoresist pattern may be formed, and a dielectric layer may be formed on the photoresist pattern. An anisotropically etch backed process may be performed on the dielectric layer to expose a substrate under the dielectric layer. Also, a bottom anti-reflection coating (ARC) layer may be formed between the dielectric layer and the substrate. The photoresist pattern may be removed. A portion from which the photoresist pattern is removed may be filled with another ARC layer and another dielectric layer, and the resultant structure may be planarized. By this process, a dielectric layer pattern twice as dense as the photoresist pattern may be formed on the substrate.
However, the above-described techniques have several problems. For example, in the first conventional method, resulting metal patterns may not form a planar surface. In the second conventional method, electrical connection between the second interconnection pattern and a substrate may be impeded. The third conventional method is a complicated patterning method, which includes a plurality of sacrificial processes, and precludes the formation of dielectric patterns.